ACOTES project: Advanced compiler technologies for embedded streaming

Streaming applications are built of data-driven, computational components, consuming and producing unbounded data streams. Streaming oriented systems have become dominant in a wide range of domains, including embedded applications and DSPs. However, programming efficiently for streaming architectures is a challenging task, having to carefully partition the computation and map it to processes in a way that best matches the underlying streaming architecture, taking into account the distributed resources (memory, processing, real-time requirements) and communication overheads (processing and delay). These challenges have led to a number of suggested solutions, whose goal is to improve the programmer’s productivity in developing applications that process massive streams of data on programmable, parallel embedded architectures. StreamIt is one such example. Another more recent approach is that developed by the ACOTES project (Advanced Compiler Technologies for Embedded Streaming). The ACOTES approach for streaming applications consists of compiler-assisted mapping of streaming tasks to highly parallel systems in order to maximize cost-effectiveness, both in terms of energy and in terms of design effort. The analysis and transformation techniques automate large parts of the partitioning and mapping process, based on the properties of the application domain, on the quantitative information about the target systems, and on programmer directives. This paper presents the outcomes of the ACOTES project, a 3-year collaborative work of industrial (NXP, ST, IBM, Silicon Hive, NOKIA) and academic (UPC, INRIA, MINES ParisTech) partners, and advocates the use of Advanced Compiler Technologies that we developed to support Embedded Streaming.Peer ReviewedPostprint (published version

Issues and challenges in development of massively-parallel heterogeneous MPSoCs based on adaptable ASIPs

The recent spectacular progress in modern Nan electronic technology enabled implementation of very complex multiprocessor systems on single chips (MPSoCs) and created a big stimulus towards development of MPSoCs for embedded applications. The increasingly complex MPSoCs are required to perform real-time computations to extremely tight schedules and to satisfy high demands regarding adaptability, as well as energy, area and cost efficiency. This results in serious design and development challenges. The opportunities created can effectively be exploited only through use of more adequate system architectures and more integrated system IP modules, supported by new effective design methods and electronic design automation tools. This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It is related to a European project ASAM being currently executed in the framework of the ARTEMIS program. It presents the results of our analysis of the main problems that have to be solved and challenges to be faced in design of such heterogeneous customizable MPSoCs for modern demanding applications

Issues and challenges in development of massively-parallel heterogeneous MPSoCs based on adaptable ASIPs

The recent spectacular progress in modern Nan electronic technology enabled implementation of very complex multiprocessor systems on single chips (MPSoCs) and created a big stimulus towards development of MPSoCs for embedded applications. The increasingly complex MPSoCs are required to perform real-time computations to extremely tight schedules and to satisfy high demands regarding adaptability, as well as energy, area and cost efficiency. This results in serious design and development challenges. The opportunities created can effectively be exploited only through use of more adequate system architectures and more integrated system IP modules, supported by new effective design methods and electronic design automation tools. This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It is related to a European project ASAM being currently executed in the framework of the ARTEMIS program. It presents the results of our analysis of the main problems that have to be solved and challenges to be faced in design of such heterogeneous customizable MPSoCs for modern demanding applications

ConvFusion A Model for Layer Fusion in Convolutional Neural Networks

The superior accuracy and appealing universality of convolutional neural networks (CNNs) as a generic algorithm for many classification tasks have made the design of energy efficient CNN accelerators an important topic in both academia and industry. Of particular interest in the design and use of CNN accelerators is the scheduling of the computational workload, which can have a major impact on the quality of the final design. The many inherently independent operations in CNNs result in a vast scheduling space however, rendering the selection of the optimal schedule(s) non-trivial. To aid in this complex task, this work introduces a generic mathematical cost model of the external memory accesses, internal memory footprint, and compute load for CNN execution schedules. The model enables fast exploration of the scheduling space, including loop tiling, loop reordering, explicit data transfer scheduling, recomputation, and, crucially, layer fusion, which recently has attracted interest as a method to reduce external memory accesses. An accompanying open source tool is released to perform schedule space exploration for CNNs using the introduced cost model. Leveraging the code generation capabilities of this tool the proposed model is validated on six real world networks, demonstrating that layer fusion can reduce the external memory accesses by more than two orders of magnitude compared to the best non-fused schedules. Confusing at first glance however, a high-level energy analysis shows that the practical benefits of layer fusion may be overestimated if other parts of the system are not tuned accordingly

Ambient Intelligence Visions and Achievements: Linking abstract ideas to real-world concepts

Ideas to Real-World Concepts Menno Lindwer , Diana Marculescu , Twan Basten , Rainer Zimmermann , Radu Marculescu , Stefan Jung , Eugenio Cantatore Philips Research, Eindhoven, The Netherlands Carnegie Mellon University, Pittsburg, PA, USA Eindhoven University of Technology, Eindhoven, The Netherlands European Commission, Brussels, Belgium Infineon Technologies, Corporate Research, Emerging Technologies, Munich, Germany Abstract The Ambient Intelligence vision is abstract and as such not useful for funding decisions, research project definition, and business plan development. This is in particular the case for the electronic design community. The European Commission intends for the EU to achieve world leadership in Information Societies technologies within ten years. To that end, it has incorporated the Ambient Intelligence vision in its Sixth Framework. Microelectronics and nanoand optical devices are seen as key technologies. Interesting chip-level challenges are found in, amongst others, explicit modeling of mobility and self-management, and novel computing substrates, based on electronic textiles or organic electronics

Scaling into Ambient Intelligence

Envision the situation that high quality information and entertainment is easily accessible to anyone, anywhere, at any time, and on any device. How realistic is this vision? And what does it require from the underlying technology? Ambient Intelligence (AmI) integrates concepts ranging from ubiquitous computing to autonomous and intelligent systems. An AmI environment will be highly dynamic in many aspects. Underlying technology must be very flexible to cope with this dynamism. Scalability of technology is only one crucial aspect. This paper explores scalability from the processing, the communication, and the software perspectives

ASAM: Automatic architecture synthesis and application mapping

This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It presents an over-view of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program. The paper briefly presents the results of our analysis of the main problems to be solved and challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to resolve the problems and address the challenges. Finally, it introduces and briefly discusses the ASAM design-flow and its main stages